A load operation may include any instruction, operation, or micro-operation to load a value from a memory, such as a cache or other memory device. In some processors a load may search a store buffer (SB) and first level data cache simultaneously in an attempt to access data in a timely manner. However, if the load hits the SB (e.g., load can be satisfied by data in the SB that has yet to be written back to a cache) the cache access was unnecessary and the power consumed in accessing the cache was wasted.
Several techniques may be used to avoid such power waste while still providing timely access to data. First, processors may serialize accesses by first searching the SB and then the data cache. However, doing so may hurt time performance if there is a SB miss. Second, the number of cache accesses may be reduced, thereby conserving power, by using hardware predictors to identify loads that do not require cache access. However, using hardware predictors may result in increased power consumption.